Chapter 5 systemverilog axi3 and axi4 monitor bfms, Inline monitor connection, Figure 5-1. inline monitor connection diagram – Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM User Manual
Page 121

Mentor VIP AE AXI3/4 User Guide, V10.2b
103
September 2013
Chapter 5
SystemVerilog AXI3 and AXI4 Monitor BFMs
This section provides information about the SystemVerilog AXI3 and AXI4 monitor BFMs.
Each BFM has an API that contains tasks and functions to configure the BFM and to access the
dynamic
during the lifetime of a transaction.
Note
Due to AXI3 protocol specification changes, for some BFM tasks, you reference the
AXI3 interface by specifying AXI instead of AXI3.
Inline Monitor Connection
The connection of a monitor BFM to a test environment differs from that of a master and slave
BFM. It is wrapped in an inline monitor interface and connected inline between a master and
slave, as shown in
. It has separate master and slave ports and monitors protocol
traffic between a master and slave. The monitor itself then has access to all the facilities
provided by the monitor BFM.
Figure 5-1. Inline Monitor Connection Diagram
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
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- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
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- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
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