Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 637)

VHDL Tutorials
Verifying a Slave DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 617
September 2013
report "master_test_program: Error: Expected data (1) at address 1, but
got " & lp.all;
end if;
In the complete Master Test Program, three subsequent read transactions are created and
executed in a similar manner to that shown in
Example 11-11 . See the VHDL AXI4 Master
BFM Test Program code listing for details.
Write Burst Transaction Creation and Execution
The code excerpt in Example 11-12 calls the create_write_transaction() procedure to create a
write burst transaction by providing the start address and burst length arguments. The actual
length of the burst on the protocol signals is 7+1=8.
Note
The burst length argument passed to the create_write_transaction() procedure is 1 less
than the number of transfers (beats) in the burst. This aligns the burst length argument
value with the value placed on the AWLEN protocol signals.
The set_data_words() procedure is then called eight times to set the data_words field of the
write transaction for each beat of the data burst. For this write transaction, all data byte lanes
contain valid data on each beat of the data burst, therefore a ‘for .. loop’ calls the
set_write_strobes() procedure to set the write_strobes fields of the transaction to 15 for each
beat of the burst.