Set_data_valid_delay(), Axi3 example – Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM User Manual
Page 311

VHDL AXI3 and AXI4 Master BFMs
set_data_valid_delay()
Mentor VIP AE AXI3/4 User Guide, V10.2b
293
September 2013
set_data_valid_delay()
This nonblocking procedure sets the data_valid_delay field for a transaction that is uniquely
identified by the transaction_id field previously created by the
procedure.
AXI3 Example
-- Create a write transaction with start address of 0.
-- Creation returns tr_id to identify the transaction.
create_write_transaction(0, tr_id, bfm_index, axi_tr_if_0(bfm_index));
-- Set the write channel WVALID delay to 3 ACLK cycles for the first data
-- phase (beat) of the tr_id transaction.
set_data_valid_delay(3, 0, tr_id, bfm_index, axi_tr_if_0(bfm_index));
-- Set the write channel WVALID delay to 2 ACLK cycles for the second data
-- phase (beat) of the tr_id transaction.
set_data_valid_delay(2, 1, tr_id, bfm_index, axi_tr_if_0(bfm_index));
Prototype
-- * = axi| axi4
-- ** = AXI | AXI4
set_data_valid_delay
(
data_valid_delay: in integer;
index : in integer; --optional
transaction_id : in integer;
bfm_id : in integer;
path_id : in *_path_t; --optional
signal tr_if : inout *_vhd_if_struct_t
);
Arguments
data_valid_delay
Write data channel WVALID delay measured in ACLK cycles
for this transaction. Default: 0.
index
(Optional) Array element index number for data_valid_delay.
transaction_id
Transaction identifier. Refer to
on page 203 for more details.
bfm_id
on page 203 for more details.
path_id
(Optional) Parallel process path identifier:
**_PATH_0
**_PATH_1
**_PATH_2
**_PATH_3
**_PATH_4
“Overloaded Procedure Common Arguments”
page 203 for more details.
tr_if
Transaction signal interface. Refer to
on page 203 for more details.
Returns
None