Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 638)

Mentor VIP AE AXI3/4 User Guide, V10.2b 618
VHDL Tutorials
Verifying a Slave DUT
September 2013
The call to set_write_data_mode() procedure configures the write burst transaction to allow the
write address phase and write data burst to start simultaneously
(AXI4_DATA_WITH_ADDRESS) when executed. The write transaction is then executed onto
the protocol signals.
Example 11-12. Write Burst Transaction Creation and Execution
-- Write data burst length of 7 to start address 16.
create_write_transaction(16, 7, tr_id, index, axi4_tr_if_0(index));
data_words(31 downto 0) := x"ACE0ACE1";
set_data_words(data_words, 0, tr_id, index, axi4_tr_if_0(index));
data_words(31 downto 0) := x"ACE2ACE3";
set_data_words(data_words, 1, tr_id, index, axi4_tr_if_0(index));
data_words(31 downto 0) := x"ACE4ACE5";
set_data_words(data_words, 2, tr_id, index, axi4_tr_if_0(index));
data_words(31 downto 0) := x"ACE6ACE7";
set_data_words(data_words, 3, tr_id, index, axi4_tr_if_0(index));
data_words(31 downto 0) := x"ACE8ACE9";
set_data_words(data_words, 4, tr_id, index, axi4_tr_if_0(index));
data_words(31 downto 0) := x"ACEAACEB";
set_data_words(data_words, 5, tr_id, index, axi4_tr_if_0(index));
data_words(31 downto 0) := x"ACECACED";
set_data_words(data_words, 6, tr_id, index, axi4_tr_if_0(index));
data_words(31 downto 0) := x"ACEEACEF";
set_data_words(data_words, 7, tr_id, index, axi4_tr_if_0(index));
for i in 0 to 7 loop
set_write_strobes(15, i, tr_id, index, axi4_tr_if_0(index));
end loop;
set_write_data_mode(AXI4_DATA_WITH_ADDRESS, tr_id, index,
axi4_tr_if_0(index));
execute_transaction(tr_id, index, axi4_tr_if_0(index));
In the complete Master Test Program, a subsequent write data burst transaction has lane 0 of the
first data beat of the burst configured to be invalid, by setting the least significant bit of the
write_strobes[0] field to zero by passing in the value of 14. See
set_write_strobes() for more
details.
set_write_strobes(14, 0, tr_id, index, axi_tr_if_0(index));
See the VHDL AXI4 Master BFM Test Program code listing for details.
Read Burst Transaction Creation and Execution
The code excerpt in Example 11-13 reads the first two data beats from the data burst that has
been previously written into the slave memory. The call to the create_read_transaction()
procedure creates the read burst transaction by providing the start address and burst length
arguments. The actual length of the burst on the protocol signals is 1+1=2.