Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 187)

SystemVerilog Tutorials
Verifying a Master DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 169
September 2013
Internal Memory
The internal memory for the slave is defined as a sparse array of 8-bits, so that each byte of data
is stored as an address/data pair.
Example 6-32. internal memory
// Storage for a memory
bit [7:0] mem [*];
do_byte_read()
The do_byte_read() function, when called, will read a data byte from the Internal Memory mem,
given an address location as shown below.
You can edit this function to modify the way the read data is extracted from the Internal
Memory.
Example 6-33. do_byte_read()
// Function : do_byte_read
// Function to provide read data byte from memory at
// particular input address
function bit[7:0] do_byte_read(addr_t addr);
return mem[addr];
endfunction
do_byte_write()
The do_byte_write() function, when called, writes a data byte to the Internal Memory mem,
given an address location as shown below.
You can edit this function to modify the way the write data is stored in the Internal Memory.
Example 6-34. do_byte_write()
// Function : do_byte_write
// Function to write data byte to memory at particular
// input address
function void do_byte_write(addr_t addr, bit [7:0] data);
mem[addr] = data;
endfunction
m_rd_addr_phase_ready_delay
The m_rd_addr_phase_ready_delay variable holds the ARREADY signal delay. The delay value
extends the length of the read address phase by a number of ACLK cycles. The starting point of
the delay is determined by the
slave_ready_delay_mode variable configuration.