Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 54)

Mentor VIP AE AXI3/4 User Guide, V10.2b 36
SystemVerilog AXI3 and AXI4 Master BFMs
Master BFM Configuration
September 2013
A master BFM has configuration fields that you can set with the set_config() function to
configure timeout factors, slave exclusive support, and setup and hold times, etc. You can also
get the value of a configuration field using the
get_config() function. The full list of
configuration fields is described in Table 3-2 below.
Table 3-2. Master BFM Configuration
Configuration Field (Note: ** = AXI or AXI4) Description
Timing Variables
**_CONFIG_SETUP_TIME The setup-time prior to the active edge
of ACLK, in units of simulator time-
steps for all signals.
1
Default: 0.
**_CONFIG_HOLD_TIME The hold-time after the active edge of
ACLK, in units of simulator time-steps
for all signals.
1
Default: 0.
**_CONFIG_MAX_TRANSACTION_TIME_FACTOR The maximum timeout duration for a
read/write transaction in clock cycles.
Default: 100000.
**_CONFIG_BURST_TIMEOUT_FACTOR The maximum delay between the
individual phases of a read/write
transaction in clock cycles. Default:
10000.
**_CONFIG_MAX_LATENCY_AWVALID_
ASSERTION_TO_AWREADY
The maximum timeout duration from
the assertion of AWVALID to the
assertion of AWREADY in clock
periods. Default: 1000.
**_CONFIG_MAX_LATENCY_ARVALID_
ASSERTION_TO_ARREADY
The maximum timeout duration from
the assertion of ARVALID to the
assertion of ARREADY in clock
periods. Default: 10000.
**_CONFIG_MAX_LATENCY_RVALID_
ASSERTION_TO_RREADY
The maximum timeout duration from
the assertion of RVALID to the
assertion of RREADY in clock periods.
Default: 10000.
**_CONFIG_MAX_LATENCY_BVALID_
ASSERTION_TO_BREADY
The maximum timeout duration from
the assertion of BVALID to the
assertion of BREADY in clock periods.
Default: 10000.
**_CONFIG_MAX_LATENCY_WVALID_
ASSERTION_TO_WREADY
The maximum timeout duration from
the assertion of WVALID to the
assertion of WREADY in clock periods.
Default 10000.