Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 316)

Mentor VIP AE AXI3/4 User Guide, V10.2b 298
VHDL AXI3 and AXI4 Master BFMs
get_data_ready_delay()
September 2013
AXI3 Example
-- Create a write transaction with start address of 0.
-- Creation returns tr_id to identify the transaction.
create_write_transaction(0, tr_id, bfm_index, axi_tr_if_0(bfm_index));
-- Get the write data channel WREADY delay the first
-- dataphase (beat) of the tr_id transaction.
get_data_ready_delay(data_ready_delay, 0, tr_id, bfm_index,
axi_tr_if_0(bfm_index));
-- Get the write data channel WREADY delay for the second
-- data phase (beat) of the tr_id transaction.
get_data_ready_delay(data_ready_delay, 1, tr_id, bfm_index,
axi_tr_if_0(bfm_index));
AXI4 Example
-- Create a write transaction with start address of 0.
-- Creation returns tr_id to identify the transaction.
create_write_transaction(0, tr_id, bfm_index, axi4_tr_if_0(bfm_index));
-- Get the write data channel WREADY delay the first
-- dataphase (beat) of the tr_id transaction.
get_data_ready_delay(data_ready_delay, 0, tr_id, bfm_index,
axi4_tr_if_0(bfm_index));
-- Get the write data channel WREADY delay for the second
-- data phase (beat) of the tr_id transaction.
get_data_ready_delay(data_ready_delay, 1, tr_id, bfm_index,
axi4_tr_if_0(bfm_index));