Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 508)

Mentor VIP AE AXI3/4 User Guide, V10.2b 488
VHDL AXI3 and AXI4 Monitor BFMs
Monitor BFM Configuration
September 2013
Table 10-2. Monitor BFM Configuration
Configuration Field Description
Timing Variables
**_CONFIG_SETUP_TIME The setup-time prior to the active edge
of ACLK, in units of simulator time-
steps for all signals.
1
Default: 0.
**_CONFIG_HOLD_TIME The hold-time after the active edge of
ACLK, in units of simulator time-steps
for all signals.
1
Default: 0.
**_CONFIG_MAX_TRANSACTION_TIME_FACTOR The maximum timeout duration for a
read/write transaction in clock cycles.
Default: 100000.
AXI_CONFIG_TIMEOUT_MAX_DATA_TRANSFER (AXI3) The maximum number of write
data beats that the AXI3 BFM can
generate as part of write data burst of
write transfer. Default: 1024.
_CONFIG_BURST_TIMEOUT_FACTOR The maximum delay between the
individual phases of a read/write
transaction in clock cycles. Default:
10000.
**_CONFIG_MAX_LATENCY_AWVALID_
ASSERTION_TO_AWREADY
The maximum timeout duration from
the assertion of AWVALID to the
assertion of AWREADY in clock.
periods. Default: 10000.
**_CONFIG_MAX_LATENCY_ARVALID_
ASSERTION_TO_ARREADY
The maximum timeout duration from
the assertion of ARVALID to the
assertion of ARREADY in clock
periods. Default:10000.
**_CONFIG_MAX_LATENCY_RVALID_
ASSERTION_TO_RREADY
The maximum timeout duration from
the assertion of RVALID to the
assertion of RREADY in clock periods.
Default: 10000.
**_CONFIG_MAX_LATENCY_BVALID_
ASSERTION_TO_BREADY
The maximum timeout duration from
the assertion of BVALID to the
assertion of BREADY in clock periods.
Default: 10000.
**_CONFIG_MAX_LATENCY_WVALID_
ASSERTION_TO_WREADY
The maximum timeout duration from
the assertion of WVALID to the
assertion of WREADY in clock periods.
Default: 10000.
Slave Attributes
**_CONFIG_SLAVE_START_ADDR Configures the start address map for
the slave.