11 register description, 1 osccal – oscillator calibration register, 2 pllcsr – pll control and status register – Rainbow Electronics ATmega64M1 User Manual
Page 35: Osccal – oscillator calibration register” on
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8209A–AVR–08/09
ATmega16M1/32M1/64M1
1.
Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
CLKPR to zero.
2.
Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
9.11
Register Description
9.11.1
OSCCAL – Oscillator Calibration Register
• Bits 7:0 – CAL7:0: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to
remove process variations from the oscillator frequency. A pre-programmed calibration value is
automatically written to this register during chip reset, giving the Factory calibrated frequency as
specified in
. The application software can write this register to change
the oscillator frequency. The oscillator can be calibrated to frequencies as specified in
. Calibration outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more
than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the
lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-
quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher
frequency than OSCCAL = 0x80.
The CAL6:0 bits are used to tune the frequency within the selected range. A setting of 0x00
gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the
range.
9.11.2
PLLCSR – PLL Control and Status Register
• Bit 7:3 – Res: Reserved Bits
These bits are reserved and always read as zero.
• Bit 2 – PLLF: PLL Factor
The PLLF bit is used to select the division factor of the PLL.
If PLLF is set, the PLL output is 64MHz.
If PLLF is clear, the PLL output is 32MHz.
• Bit 1 – PLLE: PLL Enable
Bit
7
6
5
4
3
2
1
0
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
OSCCAL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
Device Specific Calibration Value
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
PLLF
PLLE
PLOCK
PLLCSR
Read/Write
R
R
R
R
R
R/W
R/W
R
Initial Value
0
0
0
0
0
0
0/1
0