Rainbow Electronics ATmega64M1 - Manual (Page 260)

260
8209A–AVR–08/09
ATmega16M1/32M1/64M1
In case ICES1 bit ( “TCCR1B – Timer/Counter1 Control Register B” on page 126 ) is set high, the
rising edge of AC1O is the capture/trigger event of the Timer/Counter1, in case ICES1 is set to
zero, it is the falling edge which is taken into account.
Clear this bit to disable this function. In this case, no connection between the Analog Compara-
tor and the input capture function exists.
• Bit 2:0 – AC1M[2:0]: Analog Comparator 1 Multiplexer register
These 3 bits determine the input of the negative input of the analog comparator.
The different setting are shown in
Table 24-4 .
24.4.3 AC2CON – Analog Comparator 2 Control Register
• Bit 7– AC2EN: Analog Comparator 2 Enable Bit
Set this bit to enable the analog comparator 2.
Clear this bit to disable the analog comparator 2.
• Bit 6– AC2IE: Analog Comparator 2 Interrupt Enable bit
Set this bit to enable the analog comparator 2 interrupt.
Clear this bit to disable the analog comparator 2 interrupt.
• Bit 5:4 – AC2IS[1:0]: Analog Comparator 2 Interrupt Select bit
These 2 bits determine the sensitivity of the interrupt trigger.
The different setting are shown in
Table 24-1 .
Table 24-4. Analog Comparator 1 negative input selection
AC1M[2:0] Description
000 “Vref”/6.40
001 “Vref”/3.20
010 “Vref”/2.13
011 “Vref”/1.60
100 Bandgap (1.1V)
101 DAC result
110 Analog Comparator Negative Input (ACMPM pin)
111 Reserved
Bit 7 6 5 4 3 2 1 0
AC2EN AC2IE AC2IS1 AC2IS0 - AC2M2 AC2M1 AC2M0 AC2CON
Read/Write R/W R/W R/W R/W - R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0