Rainbow Electronics ATmega64M1 - Manual (Page 193)

193
8209A–AVR–08/09
ATmega16M1/32M1/64M1
• Bit 4 – BERR: Bit Error (Only in Transmission)
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine
on the whole CANSTMOB register.
The bit value monitored is different from the bit value sent.
Exceptions: the monitored recessive bit sent as a dominant bit during the arbitration field and the
acknowledge slot detecting a dominant bit during the sending of an error frame.
• Bit 3 – SERR: Stuff Error
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine
on the whole CANSTMOB register.
Detection of more than five consecutive bits with the same polarity. This flag can generate an
interrupt.
• Bit 2 – CERR: CRC Error
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine
on the whole CANSTMOB register.
The receiver performs a CRC check on every de-stuffed received message from the start of
frame up to the data field. If this checking does not match with the de-stuffed CRC field, a CRC
error is set.
• Bit 1 – FERR: Form Error
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine
on the whole CANSTMOB register.
The form error results from one or more violations of the fixed form in the following bit fields:
• CRC delimiter.
• Acknowledgment delimiter.
• EOF
• Bit 0 – AERR: Acknowledgment Error
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine
on the whole CANSTMOB register.
No detection of the dominant bit in the acknowledge slot.
20.11.2 CANCDMOB – CAN MOb Control and DLC Register
• Bit 7:6 – CONMOB[1:0]: Configuration of Message Object
These bits set the communication to be performed (no initial value after RESET).
– 00 - disable.
– 01 - enable transmission.
– 10 - enable reception.
– 11 - enable frame buffer reception
Bit 7 6 5 4 3 2 1 0
CONMOB1 CONMOB0 RPLV IDE DLC3 DLC2 DLC1 DLC0 CANCDMOB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value - - - - - - - -