Rainbow Electronics ATmega64M1 - Manual (Page 150)

150
8209A–AVR–08/09
ATmega16M1/32M1/64M1
18.16.6 POCRnRBH and POCRnRBL – PSC Output Compare RB Register
Note : n = 0 to 2 according to module number.
The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously
compared with the PSC counter value. A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the associated pin.
The Output Compare Registers are 16bit and 12-bit in size. To ensure that both the high and low
bytes are written simultaneously when the CPU writes to these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by
all the other 16-bit registers.
18.16.7 PCNF – PSC Configuration Register
• Bit 7:6 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 5 – PULOCK: PSC Update Lock
When this bit is set, the Output Compare Registers POCRnRA, POCRnSA, POCRnSB,
POCR_RB and the PSC Output Configuration Registers POC can be written without disturbing
the PSC cycles. The update of the PSC internal registers will be done if the PULOCK bit is
released to zero.
• Bit 4 – PMODE PSC Mode
Select the mode of PSC.
• Bit 3 – POPB: PSC B Output Polarity
If this bit is cleared, the PSC outputs B are active Low.
If this bit is set, the PSC outputs B are active High.
• Bit 2 – POPA: PSC A Output Polarity
If this bit is cleared, the PSC outputs A are active Low.
If this bit is set, the PSC outputs A are active High.
Bit 7 6 5 4 3 2 1 0
– – – – POCRnRB[11:8] POCRnRBH
POCRnRB[7:0] POCRnRBL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
- - PULOCK PMODE POPB POPA - - PCNF
Read/Write R R R/W R/W R/W R/W R R
Initial Value 0 0 0 0 0 0 0 0
Table 18-10. PSC Mode Selection
PMODE Description
0 One Ramp Mode (Edge Aligned)
1 Center Aligned Mode