Rainbow Electronics ATmega64M1 - Manual (Page 220)

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8209A–AVR–08/09
ATmega16M1/32M1/64M1
The user clears this bit by writing 1 in order to reset this interrupt. Resetting LERR also
resets all LINERR bits.
In UART mode, this bit is also cleared by reading LINDAT.
• Bit 2 - LIDOK: Identifier Interrupt
This bit generates an interrupt if its respective enable bit - LENIDOK - is set in LINENIR.
– 0 = No identifier,
– 1 = Slave task: Identifier present, master task: Tx Header complete.
The user clears this bit by writing 1, in order to reset this interrupt.
• Bit 1 - LTXOK: Transmit Performed Interrupt
This bit generates an interrupt if its respective enable bit - LENTXOK - is set in LINENIR.
– 0 = No Tx,
– 1 = Tx Response complete.
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by writing LINDAT.
• Bit 0 - LRXOK: Receive Performed Interrupt
This bit generates an interrupt if its respective enable bit - LENRXOK - is set in LINENIR.
– 0 = No Rx
– 1 = Rx Response complete.
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by reading LINDAT.
21.6.3 LINENIR – LIN Enable Interrupt Register
• Bits 7:4 - Res: Reserved
These bits are reserved for future use. For compatibility with future devices, they must be
written to zero when LINENIR is written.
• Bit 3 - LENERR: Enable Error Interrupt
– 0 = Error interrupt masked,
– 1 = Error interrupt enabled.
• Bit 2 - LENIDOK: Enable Identifier Interrupt
– 0 = Identifier interrupt masked,
– 1 = Identifier interrupt enabled.
• Bit 1 - LENTXOK: Enable Transmit Performed Interrupt
– 0 = Transmit performed interrupt masked,
Bit 7 6 5 4 3 2 1 0
- - - - LENERR LENIDOK LENTXOK LENRXOK LINENIR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0