Rainbow Electronics ATmega64M1 - Manual (Page 217)

217
8209A–AVR–08/09
ATmega16M1/32M1/64M1
21.5.15 Data Management
21.5.15.1 LIN FIFO Data Buffer
To preserve register allocation, the LIN data buffer is seen as a FIFO (with address pointer
accessible). This FIFO is accessed via the LINDX[2..0] field of LINSEL register through the LIN-
DAT register.
LINDX[2..0], the data index, is the address pointer to the required data byte. The data byte can
be read or written. The data index is automatically incremented after each LINDAT access if the
LAINC (active low) bit is cleared. A roll-over is implemented, after data index=7 it is data
index=0. Otherwise, if LAINC bit is set, the data index needs to be written (updated) before each
LINDAT access.
The first byte of a LIN frame is stored at the data index=0, the second one at the data index=1,
and so on. Nevertheless, LINSEL must be initialized by the user before use.
21.5.15.2 UART Data Register
The LINDAT register is the data register (no buffering - no FIFO). In write access, LINDAT will be
for data out and in read access, LINDAT will be for data in.
In UART mode the LINSEL register is unused.
21.5.16 OCD Support
This chapter describes the behavior of the LIN/UART controller stopped by the OCD (i.e. I/O
view behavior in AVR Studio)
1. LINCR:
- LINCR[6..0] are R/W accessible,
- LSWRES always is a self-reset bit (needs 1 micro-controller cycle to execute)
2. LINSIR:
- LIDST[2..0] and LBUSY are always Read accessible,
- LERR & LxxOK bit are directly accessible (unlike in execution, set or cleared directly
by writing 1 or 0).
- Note that clearing LERR resets all LINERR bits and setting LERR sets all LINERR
bits.
3. LINENR:
- All bits are R/W accessible.
4. LINERR:
- All bits are R/W accessible,
- Note that LINERR bits are ORed to provide the LERR interrupt flag of LINSIR.
5. LINBTR:
- LBT[5..0] are R/W access only if LDISR is set,
- If LDISR is reset, LBT[5..0] are unchangeable.
6. LINBRRH & LINBRRL:
- All bits are R/W accessible.
7. LINDLR:
- All bits are R/W accessible.
8. LINIDR:
- LID[5..0] are R/W accessible,
- LP[1..0] are Read accessible and are always updated on the fly.
9. LINSEL:
- All bits are R/W accessible.