10 canbt3 – can bit timing register 3, 11 cantcon – can timer control register, Section • “bit 0 – smp: sam – Rainbow Electronics ATmega64M1 User Manual
Page 190
190
8209A–AVR–08/09
ATmega16M1/32M1/64M1
20.10.10 CANBT3 – CAN Bit Timing Register 3
• Bit 7– Res: Reserved
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT3 is written.
• Bit 6:4 – PHS2[2:0]: Phase Segment 2
This phase is used to compensate for phase edge errors. This segment may be shortened by
the re-synchronization jump width. PHS2[2:0] shall be 1 and
≤
PHS1[2..0] (c.f.
and
Section 20.5.3 “Baud Rate” on page 173
• Bit 3:1 – PHS1[2:0]: Phase Segment 1
This phase is used to compensate for phase edge errors. This segment may be lengthened by
the re-synchronization jump width.
• Bit 0 – SMP: Sample Point(s)
This option allows to filter possible noise on TxCAN input pin.
– 0 - the sampling will occur once at the user configured sampling point - SP.
– 1 - with three-point sampling configuration the first sampling will occur two
T
clk
IO
clocks before the user configured sampling point - SP, again at one
T
clk
IO
clock
before SP and finally at SP. Then the bit level will be determined by a majority vote of
the three samples.
‘SMP=1’ configuration is not compatible with ‘BRP[5:0]=0’ because TQ =
T
clk
IO
.
If BRP = 0, SMP must be cleared.
20.10.11 CANTCON – CAN Timer Control Register
• Bit 7:0 – TPRSC[7:0]: CAN Timer Prescaler
Prescaler for the CAN timer upper counter range 0 to 255. It provides the clock to the CAN timer
if the CAN controller is enabled.
T
clk
CANTIM
=
T
clk
IO
x 8 x (CANTCON [7:0] + 1)
Bit
7
6
5
4
3
2
1
0
-
PHS22
PHS21
PHS20
PHS12
PHS11
PHS10
SMP
CANBT3
Read/Write
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
-
0
0
0
0
0
0
0
Tphs2 = Tscl x (PHS2 [2:0] + 1)
Tphs1 = Tscl x (PHS1 [2:0] + 1)
Bit
7
6
5
4
3
2
1
0
TPRSC7
TPRSC6
TPRSC5
TPRSC4
TPRSC3
TPRSC2
TRPSC1
TPRSC0
CANTCON
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0