Rainbow Electronics ATmega64M1 - Manual (Page 140)

140
8209A–AVR–08/09
ATmega16M1/32M1/64M1
Figure 18-7. Controlled Start and Stop Mechanism in Centered Mode
Note: See “PCTL – PSC Control Register” on page 151. (PCCYC = 1)
18.6 Update of Values
To avoid unasynchronous and incoherent values in a cycle, if an update of one of several values
is necessary, all values are updated at the same time at the end of the cycle by the PSC. The
new set of values is calculated by sofware and the update is initiated by software.
Figure 18-8. Update at the end of complete PSC cycle.
The software can stop the cycle before the end to update the values and restart a new PSC
cycle.
18.6.1 Value Update Synchronization
New timing values or PSC output configuration can be written during the PSC cycle. Thanks to
LOCK configuration bit, the new whole set of values can be taken into account after the end of
the PSC cycle.
When LOCK configuration bit is set, there is no update. The update of the PSC internal registers
will be done at the end of the PSC cycle if the LOCK bit is released to zero.
The registers which update is synchronized thanks to LOCK are POC, POM2, POCRnSAH/L,
POCRnRAH/L, POCRnSBH/L and POCRnRBH/L.
See these register’s description starting on page 149 .
PSCOUTnA
PSCOUTnB
PSC Counter
POCRnRB
POCRnSA
POCRnSB
0
Run
Software
PSC
Regulation Loop
Calculation Writting in
PSC Registers
Cycle
With Set i Cycle
With Set i Cycle
With Set i Cycle
With Set i
Cycle
With Set j
End of Cycle
Request for
an Update