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21 lcd display register 18 (lcd18, m2[1dh]), 22 lcd display register 19 (lcd19, m2[1eh]), 23 lcd display register 20 (lcd20, m2[1fh]) – Maxim Integrated MAXQ Family Users Guide: MAXQ2010 Supplement User Manual

Page 99: 3 lcd controller operation modes, 4 lcd drive voltages, 5 selecting the lcd display mode, 6 segment pin configuration, Maxq family user’s guide: maxq2010 supplement

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MAXQ Family User’s Guide:

MAXQ2010 Supplement

20-7

20.2.21 LCD Display Register 18 (LCD18, M2[1Dh])

20.2.22 LCD Display Register 19 (LCD19, M2[1Eh])

20.2.23 LCD Display Register 20 (LCD20, M2[1Fh])

20.3 LCD Controller Operation Modes

The LCD controller defaults to suspended mode (OPM = 0, DPE = x) on power-up. In this mode, the LCD controller is
completely shut down to conserve power. Any pins that are configured for LCD operation (as well as any dedicated
LCD segment/common pins) are driven by a weak pullup to V

DDIO

.

Setting the OPM bit to 1 places the LCD controller into normal operating mode. In this mode, the LCD segment and
common drivers generate waveforms to display the contents of display register memory if the DPE bit is set to 1. If DPE
is set to 0, the LCD controller generates waveforms to turn all segments off.

20.4 LCD Drive Voltages

The LCD controller provides internal voltage-divider resistors to generate the voltage bias levels needed for the LCD
display control. The top voltage level, V

LCD

, must be provided by an external supply. As shown in Figure 20-2, no

external connections (other than the power supply to V

LCD

) are needed for static and 1/3 bias modes. For 1/2 bias

mode, V

LCD1

and V

LCD2

must be shunted together externally.

20.5 Selecting the LCD Display Mode

The DUTY1 and DUTY0 bits select one of four possible display modes for the LCD controller as shown in Table 20-1.
The display mode required for a given application depends on the number of segments needed and the multiplexing
and voltage bias requirements for a given LCD display.

20.6 Segment Pin Configuration

The PCF[4:0] bits in the LCFG register are used to switch five banks of eight pins (port 0, port 1, port 2, port 3, and
port 4) between LCD segment display mode and general-purpose port pin mode. Because all the PCF bits default to
0 on reset, all pins that share LCD segment and port pin capability act as port pins by default. To enable these pins to
be used for LCD segment display, the PCF bits must be set appropriately, and the LCD controller must be in normal
operational mode.

Bit #

7

6

5

4

3

2

1

0

Reset

0

0

0

0

0

0

0

0

Access

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rw

rw

rw

rw

rw

Bit #

7

6

5

4

3

2

1

0

Reset

0

0

0

0

0

0

0

0

Access

rw

rw

rw

rw

rw

rw

rw

rw

Bit #

7

6

5

4

3

2

1

0

Reset

0

0

0

0

0

0

0

0

Access

rw

rw

rw

rw

rw

rw

rw

rw