Maxim Integrated MAXQ Family Users Guide: MAXQ2010 Supplement - Manual (Page 20)

MAXQ Family User’s Guide:
MAXQ2010 Supplement
2-8
When the system clock source is switched back from the FLL to the high-frequency oscillator by clearing FLLSL to
zero, the FLL is still used as the system clock source until the warmup period has completed for the high-frequency
oscillator. This is reflected by the value of the FLLMD bit, which remains at 1 until the warmup for the high-frequency
oscillator has completed and the clock switches over, at which point FLLMD switches to 0.
2.7 Interrupts
In general, interrupt handling on the MAXQ2010 operates as described in the MAXQ Family User’s Guide. All interrupt
sources have the same priority, and all interrupts cause program execution to branch to the location specified by the
Interrupt Vector (IV) register, which defaults to 0000h.
Table 2-2 lists all possible interrupt sources for the MAXQ2010, along with their corresponding module interrupt enable
bits, local interrupt enable bits, and interrupt flags.
• Each module interrupt enable bit, when cleared to 0, blocks interrupts originating in that module from being acknowl-
edged. When the module interrupt enable bit is set to 1, interrupts from that module are acknowledged (unless all
interrupts have been disabled globally).
• Each local interrupt enable bit, when cleared to 0, disables the corresponding interrupt. When the local interrupt-
enable bit is set to 1, the interrupt is triggered whenever its interrupt flag is set to 1 by hardware or by software.
• Each interrupt flag bit, when set to 1, causes its corresponding interrupt to trigger. Interrupt flag bits are typically set
by hardware and must be cleared by software (generally in the interrupt handler routine).
Note that for an interrupt to fire, the following five conditions must exist:
• Interrupts must be enabled globally by setting IGE (IC.0) to 1.
• The module interrupt enable bit for the interrupt source’s module must be set to 1.
• The local interrupt enable bit for the specific interrupt source must be set to 1.
• The interrupt flag for the interrupt source must be set to 1. Typically, this is done by hardware when the condition
that requires interrupt service occurs.
• The interrupt-in-service (INS) bit must be cleared to 0. This bit is set automatically upon vectoring to the interrupt
handler (IV) address and cleared automatically upon exit (RETI/POPI), so the only reason to clear this bit manually
(inside the interrupt handler routine) is to allow nested interrupt handling.
Table 2-2. Interrupt Sources and Control Bits
INTERRUPT MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT FLAG
Watchdog Interrupt IMS (IMR.7) EWDI (WDCN.6) WDIF (WDCN.3)
External Interrupt 0 (P0.0) IM0 (IMR.0) EX0 (EIE0.0) IE0 (EIF0.0)
External Interrupt 1 (P0.1) IM0 (IMR.0) EX1 (EIE0.1) IE1 (EIF0.1)
External Interrupt 2 (P0.2) IM0 (IMR.0) EX2 (EIE0.2) IE2 (EIF0.2)
External Interrupt 3 (P0.3) IM0 (IMR.0) EX3 (EIE0.3) IE3 (EIF0.3)
External Interrupt 4 (P0.4) IM0 (IMR.0) EX4 (EIE0.4) IE4 (EIF0.4)
External Interrupt 5 (P0.5) IM0 (IMR.0) EX5 (EIE0.5) IE5 (EIF0.5)
External Interrupt 6 (P0.6) IM0 (IMR.0) EX6 (EIE0.6) IE6 (EIF0.6)
External Interrupt 7 (P0.7) IM0 (IMR.0) EX7 (EIE0.7) IE7 (EIF0.7)
RTC Time-of-Day Alarm IM0 (IMR.0) ADE (RCNT.1) ALDF (RCNT.6)
RTC Subsecond Alarm IM0 (IMR.0) ASE (RCNT.2) ALSF (RCNT.7)
External Interrupt 8 (P5.0) IM1 (IMR.1) EX8 (EIE1.0) IE8 (EIF1.0)
External Interrupt 9 (P5.1) IM1 (IMR.1) EX9 (EIE1.1) IE9 (EIF1.1)
External Interrupt 10 (P5.2) IM1 (IMR.1) EX10 (EIE1.2) IE10 (EIF1.2)
External Interrupt 11 (P5.3) IM1 (IMR.1) EX11 (EIE1.3) IE11 (EIF1.3)
External Interrupt 12 (P5.4) IM1 (IMR.1) EX12 (EIE1.4) IE12 (EIF1.4)