Maxim Integrated MAXQ Family Users Guide: MAXQ2010 Supplement - Manual (Page 126)

MAXQ Family User’s Guide:
MAXQ2010 Supplement
22-3
Bit 4: I 2 C Timeout Interrupt Flag (I2CTOI). This bit is set to 1 if either the I 2 C controller cannot generate a START
condition or the I 2 C SCL low time has expired the timeout value specified in the I2CTO register. This happens when
the I 2 C controller is operating in master mode and some other device on the bus is using the bus or holding SCL low
for an extended period of time. This bit must be cleared to 0 by software once set. Setting this bit to 1 by software
causes an interrupt if enabled.
Bit 3: I
2 C Clock Stretch Interrupt Flag (I2CSTRI). This bit indicates that the I 2 C controller is operating with clock
stretching enabled and is holding the SCL clock signal low. The I 2 C controller releases SCL after this bit has been
cleared to 0. Setting this bit to 1 by hardware causes an interrupt if enabled. This bit must be cleared to 0 by software
once set. This bit is set by hardware only.
Bit 2: I
2 C Receive Ready Interrupt Flag (I2CRXI). This bit indicates that a data byte has been received in the I 2 C
buffer. This bit must be cleared by software once set. Setting this bit to 1 by hardware causes an interrupt if enabled.
This bit is set by hardware only.
Bit 1: I
2 C Transmit Complete Interrupt Flag (I2CTXI). This bit indicates that an address or a data byte has been suc-
cessfully shifted out and the I 2 C controller has received an acknowledgment from the receiver (NACK or ACK). This bit
must be cleared by software once set. Setting this bit to 1 by software causes an interrupt if enabled.
Bit 0: I
2 C START Interrupt Flag (I2CSRI). This bit is set to 1 when a START condition (S or Sr) is detected. This bit
must be cleared to 0 by software once set. Setting this bit to 1 by software causes an interrupt if enabled.
22.1.3 Interrupt Enable Register (I2CIE, M3[02h])
Bits 15:12, 10: Reserved. Read returns 0.
Bit 11: I
2 C STOP Interrupt Enable (I2CSPIE). Setting this bit to 1 causes an interrupt to the CPU when a STOP condi-
tion is detected (I2CSPI = 1). Clearing this bit to 0 disables the STOP detection interrupt from generating.
Bit 9: I
2 C Receiver Overrun Interrupt Enable (I2CROIE). Setting this bit to 1 causes an interrupt to the CPU when a
receiver overrun condition is detected (I2ROI = 1). Clearing this bit to 0 disables receiver overrun detection interrupt
from generating.
Bit 8: I
2 C General Call Interrupt Enable (I2CGCIE). Setting this bit to 1 generates an I2CGCI (general call interrupt)
to the CPU when general call is enabled (I2CGCEN = 1). Clearing this bit to 0 disables general call interrupt from
generating.
Bit 7: I
2 C NACK Interrupt Enable (I2CNACKIE). Setting this bit to 1 causes an interrupt to the CPU when a NACK is
detected (I2CNACKI = 1). Clearing this bit to 0 disables NACK detection interrupt from generating.
Bit 6: I
2 C Arbitration Loss Enable (I2CALIE). Setting this bit to 1 causes an interrupt to the CPU when the I 2 C master
loses in an arbitration (I2CALI = 1). Clearing this bit to 0 disables arbitration loss interrupt from generating.
Bit 5: I
2 C Slave Address Match Interrupt Enable (I2CAMIE). Setting this bit to 1 causes an interrupt to the CPU
when the I 2 C controller detects an address that matches the I2CSLA value (I2CAMI = 1). Clearing this bit to 0 disables
address match interrupt from generating.
Bit 4: I
2 C Timeout Interrupt Enable (I2CTOIE). Setting this bit to 1 causes an interrupt to the CPU when a timeout
condition is detected (I2CTOI = 1). Clearing this bit to 0 disables timeout interrupt from generating. Bit 3: I 2 C Clock
Bit # 15 14 13 12 11 10 9 8
Name — — — — I2CSPIE — I2CROIE I2CGCIE
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw r rw rw
Bit # 7 6 5 4 3 2 1 0
Name I2CNACKIE I2CALIE I2CAMIE I2CTOIE I2CSTRIE I2CRXIE I2CTXIE I2CSRIE
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw