Maxim Integrated MAXQ Family Users Guide: MAXQ2010 Supplement - Manual (Page 44)

MAXQ Family User’s Guide:
MAXQ2010 Supplement
6-6
6.1.6 Port 5 Direction Register (PD5, M1[11h])
Each of the bits in this register controls the input/output direction of a port pin (P5.0 to P5.6) as follows:
0 = The port pin is in input mode, either with a weak pullup (if PO = 1) or three-stated (if PO = 0).
1 = The port pin is in output mode, with the output level to drive given by PO.
6.1.7 Port 6 Direction Register (PD6, M1[12h])
Each of the bits in this register controls the input/output direction of a port pin (P6.0 to P6.7) as follows:
0 = The port pin is in input mode, either with a weak pullup (if PO = 1) or three-stated (if PO = 0).
1 = The port pin is in output mode, with the output level to drive given by PO.
6.1.8 Port 0 Output Register (PO0, M0[00h])
Bits 7:0: Port 0 Output. This register stores the data that is output on any of the pins of port 0 that have been defined
as output pins. If the port pins are in input mode, this register controls the weak pullup for each pin. Changing the data
direction of any pins for this port (through register PD0) does not affect the value in this register.
6.1.9 Port 1 Output Register (PO1, M0[01h])
Bits 7:0: Port 1 Output. This register stores the data that is output on any of the pins of port 1 that have been defined
as output pins. If the port pins are in input mode, this register controls the weak pullup for each pin. Changing the data
direction of any pins for this port (through register PD1) does not affect the value in this register.
Bit # 7 6 5 4 3 2 1 0
Name — PD5
Reset 0 0 0 0 0 0 0 0
Access r rw rw rw rw rw rw rw
Bit # 7 6 5 4 3 2 1 0
Name PD6
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
Bit # 7 6 5 4 3 2 1 0
Name PO0
Reset 1 1 1 1 1 1 1 1
Access rw rw rw rw rw rw rw rw
Bit # 7 6 5 4 3 2 1 0
Name PO1
Reset 1 1 1 1 1 1 1 1
Access rw rw rw rw rw rw rw rw