Maxim Integrated MAXQ Family Users Guide: MAXQ2010 Supplement - Manual (Page 127)

MAXQ Family User’s Guide:
MAXQ2010 Supplement
22-4
Stretch Interrupt Enable (I2CSTRIE). Setting this bit to 1 generates an interrupt to the CPU when the clock stretch
interrupt flag is set (I2CSTRI = 1). Clearing this bit disables the clock stretch interrupt from generating.
Bit 2: I
2 C Receive Ready Interrupt Enable (I2CRXIE). Setting this bit to 1 causes an interrupt to the CPU when the
receive interrupt flag is set (I2CRXI = 1). Clearing this bit to 0 disables the receive interrupt from generating.
Bit 1: I
2 C Transmit Complete Interrupt Enable (I2CTXIE). Setting this bit to 1 causes an interrupt to the CPU when
the transmit interrupt flag is set (I2CTXI = 1). Clearing this bit to 0 disables the transmit interrupt from generating.
Bit 0: I
2 C START Interrupt Enable (I2CSRIE). Setting this bit to 1 causes an interrupt to the CPU when a START condi-
tion is detected (I2CSRI = 1). Clearing this bit to 0 disables the START detection interrupt from generating.
22.1.4 I 2 C Control Register (I2CCN, M3[0Ch])
Bit 15: I 2 C Reset (I2CRST). Setting this bit to 1 aborts the current transaction and resets the I 2 C controller. This bit is
set to 1 by software and is only cleared to 0 by hardware after the reset or when I2CEN = 0.
Bits 14:10, 3: Reserved. Read returns 0.
Bit 9: I
2 C Clock Stretch Enable (I2CSTREN). Setting this bit to 1 stretches the clock (holds SCL low) at the end of the
clock cycle specified in I2CSTRS. Clearing this bit disables clock stretching.
Bit 8: I
2 C General Call Enable (I2CGCEN). Setting this bit to 1 enables the I 2 C to respond to a general call address
(address = 0000 0000). Clearing this bit to 0 prevents the I 2 C from responding to the general call address.
Bit 7: I 2 C STOP Enable (I2CSTOP). Setting this bit to 1 generates a STOP condition. This bit automatically is self-
cleared to 0 after the STOP condition has been generated.
In master mode, setting this bit can also start the timeout timer if enabled. If the timeout timer expires before the STOP
condition can be generated, a timeout interrupt is generated to the CPU if enabled. The I2CSTOP bit is also cleared
to 0 by the timeout event.
Note that this bit has no effect when the I
2 C is operating in slave mode (I2CMST = 0), and is reset to 0 when I2CMST
= 0 or I2CEN = 0. Setting the I2CSTOP bit to 1 while I2CSTART = 1 is an invalid operation and is ignored, leaving
I2CSTOP bit cleared to 0.
Bit 6: I
2 C START (I2CSTART). Setting this bit automatically generates a START condition when the bus is free or
generates a repeated START condition during a transfer where the I 2 C module is operating as the master. This bit is
automatically self-cleared to 0 after the START condition has been generated. If the I 2 C START interrupt is enabled, a
START condition generates an interrupt to the CPU.
In master mode, setting this bit can also start the timeout timer if enabled. If the timeout timer expires before the START
condition can be generated, a timeout interrupt is generated to the CPU if enabled. The I2CSTART bit is also cleared
to 0 by the timeout event.
Note 1: I2CSTART and I2CSTOP are mutually exclusive and reset to 0 when I2CMST = 0 or I2CEN = 0.
Note 2: I2CRST is reset to 0 when I2CEN = 0.
Note 3: Writes to I2CMST, I2CMODE, and I2CEN are ignored when I2CBUSY = 1.
Note 4: If I2CRST = 1, I2CEN can be written when I2CBUSY = 1.
Note 5: Write to I2CACK is ignored if I2RST = 1.
Bit # 15 14 13 12 11 10 9 8
Name I2CRST — — — — — I2CSTREN I2CGCEN
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
Bit # 7 6 5 4 3 2 1 0
Name I2CSTOP I2CSTART I2CACK I2CSTRS — I2CMODE I2CMST I2CEN
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw