Maxim Integrated MAXQ Family Users Guide: MAXQ2010 Supplement - Manual (Page 133)

MAXQ Family User’s Guide:
MAXQ2010 Supplement
23-2
Bits 14:10: Reserved
Bits 9:8: 32kHz Oscillator Mode (32KMD[1:0]). These two bits determine the 32kHz oscillator operating mode as
follows:
• 32KMD[1:0] = 00b: Always operate in noise immune mode.
• 32KMD[1:0] = 01b: Always operate in quiet mode.
• 32KMD[1:0] = 10b: Operate in noise immune mode normally and switch to quiet mode on stop mode entry. Wait for
the 32kHz oscillator to warm up before exiting stop mode. (Note: This setting should not be used on devices of
rev B3 or earlier; refer to device errata for more details.)
• 32KMD[1:0] = 11b: Operate in noise immune mode normally and switch to quiet mode on stop mode entry. When
exiting stop mode, do not wait for the 32kHz oscillator to warm up.
Changing the value of these bits when the 32kHz clock is enabled (X32D = 0) resets the 32KRDY bit to 0 if the new
setting requires the 32kHz oscillator to warm up.
Bit 7: Brownout-Detection Disable (BOD). This bit controls whether DVDD brownout detection is enabled during stop
mode only. (Brownout detection is always enabled outside of stop mode.) Note that this setting is independent from
the SVM settings.
0 = Brownout detection is enabled during stop mode.
1 = If REGEN = 0, brownout detection is disabled during stop mode to conserve power. If REGEN = 1, brownout detec-
tion is still enabled during stop mode, regardless of the BOD bit setting.
Bit 6: Regulator Enable (REGEN). This bit controls whether the internal 1.8V regulator is enabled during stop mode
only. (The internal regulator is always enabled outside of stop mode.)
0 = The internal regulator is disabled during stop mode to conserve power.
1 = The internal regulator is enabled during stop mode.
Bit 5: 32kHz Bypass Enable (32KBYP). Setting this bit to 1 disables the 32kHz crystal oscillator, allowing a 32kHz
external clock to be provided at 32KIN. Clearing this bit to 0 enables the 32kHz crystal oscillator, allowing it to run
normally. This bit has no effect when X32D = 1.
Bit 4: High-Frequency Crystal Oscillator Disable (HFXD). Setting this bit to 1 disables the high-frequency crystal
oscillator on the MAXQ2010. However, a high-frequency external clock can still be provided at HFXIN. Clearing this bit
to 0 enables the high-frequency crystal oscillator.
Bit 3: 32kHz Clock Ready (32KRDY). This read-only bit indicates the current status of the 32kHz clock.
0 = The 32kHz clock is either disabled (X32D = 1) or is in the process of warming up.
1 = The 32kHz clock is ready for use.
Note: Software should check that 32KRDY = 1 before enabling any peripherals (RTC, LCD) that use the 32kHz
clock as a time base. Failure to do so can compromise timing accuracy.
Bit 2: 32kHz Clock Disable (X32D). Setting this bit to 1 completely disables the 32kHz clock. When X32D = 1, the
32kHz crystal oscillator is shut down, and no external 32kHz clock input is accepted. Clearing this bit to 0 allows the
32kHz clock to operate normally, with its source (crystal oscillator or external clock) selected by the 32KBYP bit.
Note: If X32D is set to 1 and the RTC is in use, ACS must be set to 1 for proper operation. Similarly, if X32D is
set to 1 and the LCD is in use, LCCS must be set to 1 for proper operation. However, even with these settings,
if X32D = 1, both the LCD and the RTC are automatically suspended upon entry to stop mode.
Bit 1: FLL Locked (FLOCK). This read-only bit indicates the current status of the FLL.
0 = The FLL is disabled or is still in the process of warming up.
1 = The FLL has locked to the 32kHz input and is ready for use.
Bit 0: Frequency-Lock Loop Enable (FLLEN). Setting this bit to 1 enables the FLL (if it is not already running) and
causes it to lock to the 32kHz input. Clearing this bit to 0 disables the FLL unless it is currently providing the system
clock.