Maxim Integrated MAXQ Family Users Guide: MAXQ2010 Supplement - Manual (Page 59)

MAXQ Family User’s Guide:
MAXQ2010 Supplement
11-1
ADDENDUM TO SECTION 11: SERIAL PERIPHERAL INTERFACE
(SPI) MODULE
The MAXQ2010 provides a serial peripheral interface (SPI) module, which operates as described in the MAXQ Family
User’s Guide.
11.1 SPI Input/Output Pins and Control Registers
Table 11-1. SPI Input and Output Pins
Table 11-2. SPI Control Registers
11.2 SPI Code Examples
11.2.1 SPI Example 1: Transmitting Data in Master Mode
move PD5.2, #1 ; Chip select for slave device
move PO5.2, #1 ; Start high
move SPICN, #03h ; Enable SPI in master mode
move SPICF, #00h ; Sample data at clock rising edge, 8 bit character
move SPICK, #63 ; SPI clock = sysclk/128
move PO5.2, #0 ; Drive chip select low
move SPIB, #12h ; Transmit byte
call waitXfer
move SPIB, #34h ; Transmit byte
call waitXfer
move PO5.2, #1 ; Release chip select
....
waitXfer:
move C, SPICN.6 ; Wait for transfer to complete
jump NC, waitXfer
move SPICN.6, #0 ; Clear transfer flag
ret
SPI INTERFACE FUNCTION PIN MULTIPLEXED WITH GPIO
SSEL: Slave Select 60 P5.3
SCLK: Slave Clock 58 P5.5
MOSI: Master Out-Slave In 59 P5.4
MISO: Master In-Slave Out 57 P5.6
REGISTER ADDRESS FUNCTION
SPICN M1[15h] SPI Control Register. Enable, master/slave-mode select, and status and interrupt flags.
SPICF M1[16h] SPI Configuration Register. Clock polarity/phase, character length, and interrupt enable.
SPICK M1[17h] SPI Clock Register. Master baud rate = 0.5 x Sysclk/(SPICK + 1).
SPIB M1[03h] SPI Data Buffer. Writes go to the SPI write buffer; reads come from the SPI read buffer.