Maxim Integrated MAXQ Family Users Guide: MAXQ2010 Supplement - Manual (Page 38)

MAXQ Family User’s Guide:
MAXQ2010 Supplement
5-6
Table 5-3. Peripheral Register Bit Reset Values (continued)
Note: Bits marked as “s” have special behavior upon reset; see the register descriptions for details.
REG
BIT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TB0C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TB1R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TB1C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TB2R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TB2C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TB0CN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TB0V 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TB1CN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TB1V 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TB2CN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TB2V 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADCN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADDATA s s s s s s s s s s s s s s s s