Maxim Integrated MAXQ Family Users Guide: MAXQ2010 Supplement - Manual (Page 130)

MAXQ Family User’s Guide:
MAXQ2010 Supplement
22-7
22.2 I 2 C Code Examples
22.2.1 I 2 C Example 1: Master Mode Transmit
; I2C configured as master, transmit to slave address 08h
; Setup for Master Mode Transmit
move I2CCN, #003h ; I2CEN = 1, I2CMST = 1
call wait_busy ; Polling routine to wait for I2CBUSY to clear
move I2CCN, #043h ; I2CEN = 1, I2CMST = 1, I2CMODE = 0, I2CSTART = 1
call wait_start ; Polling routine to wait for I2CSTART to clear
call wait_busy ; Polling routine to wait for I2CBUSY to clear
move I2CIE.1, #01h ; Enable Transmit Complete Interrupt
move I2CBUF, #008h ; Slave address set to 08h
call wait_tx_complete ; Wait for transmit interrupt
;; Verify ACK from slave
move ACC, I2CST ; Move I2C Status Register to accumulator
and #080h ; Check for NACK bit set in status register
cmp #000h
jump ne, FAIL ; If NACK bit set, handle retransmission, else continue
move I2CBUF, #0aah ; Byte to transmit
call wait_tx_complete ; Wait for transmit interrupt
22.2.2 I 2 C Example 2: Master Mode Receive
; I2C configured as master, receive from slave address 08h:
; Setup for Master Mode Receive
move I2CCN, #047h
; I2CEN = 1, I2CMST = 1, I2CMODE = 1, I2CSTART = 1
call wait_start ; Polling routine to wait for I2CSTART to clear
call wait_busy ; Polling routine to wait for I2CBUSY to clear
move I2CIE.2, #01h ; Enable Receive Ready Interrupt
move I2CBUF, #008h ; Slave address set to 08h
call wait_tx_complete ; Wait for transmit interrupt
call wait_rxbuf ; Wait for receive interrupt
;; Byte received in I2CBUF, clear I2C interrupt flag and wait for next interrupt