Maxim Integrated MAXQ Family Users Guide: MAXQ2010 Supplement - Manual (Page 13)

MAXQ Family User’s Guide:
MAXQ2010 Supplement
2-1
ADDENDUM TO SECTION 2: ARCHITECTURE
The MAXQ2010 shares the common architecture features with other members of the MAXQ microcontroller family.
Details are discussed in the following sections.
2.1 Instruction Set
This device uses the standard 16-bit MAXQ20 core instruction set as described in the MAXQ Family User’s Guide.
2.2 Harvard Memory Architecture
Program memory, data memory, and register space follow the Harvard architecture model. Each type of memory
is kept separate and is accessed by a separate bus, allowing different word lengths for different types of memory.
Registers can be either 8 bits or 16 bits in width. Program memory is 16 bits in width to accommodate the standard
MAXQ20 16-bit instruction set. Data memory is also 16 bits in width, but can be accessed in 8-bit or 16-bit modes for
maximum flexibility.
The MAXQ2010 includes a flexible memory-management unit (MMU) that allows code to be executed from either the
program flash, the utility ROM, or the internal data SRAM. Any of these three memory spaces can also be accessed
in data space at any time, with the single restriction that the physical memory area that is currently being used as pro-
gram space cannot be simultaneously read from in data space. In the event that it is necessary to read data from the
program segment that is currently in use (for example, when executing code from program flash that utilizes a lookup
table also located in program flash), standardized data transfer functions provided in the utility ROM can be used to
do so. See Section 24: Utility ROM for more details.
2.3 Register Space
The MAXQ2010 contains the standard set of MAXQ20 system registers as described in the MAXQ Family User’s Guide,
but with differences noted in this guide where they exist.
Peripheral register space (modules 0 to 4) contains registers that are used to access the following peripherals:
• 12-bit SAR ADC converter with up to eight single-ended or four differential input channels
• General-purpose 8-bit I/O ports (P0 to P6)
• External interrupts (up to 23)
• Three programmable Type B timer/counters
• Two serial USART interfaces
• I
2 C interface
• SPI interface
• Hardware multiplier
• Real-time clock (RTC)
• LCD controller
The lower 8 bits of all registers in modules 0 to 4 (as well as the AP module M8) are bit addressable.