Maxim Integrated MAXQ Family Users Guide: MAXQ2010 Supplement - Manual (Page 25)

MAXQ Family User’s Guide:
MAXQ2010 Supplement
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• An ADC conversion is initiated by setting ADCONV to 1.
• Active debug mode is entered either by a breakpoint match or direct issuance of the debug command from back-
ground mode.
As described in the MAXQ Family User’s Guide, if any of these conditions is true (a switchback source is active) and
the SWB bit has been set, the PMME bit cannot be set to enter power-management mode.
2.9.3 Stop Mode
Stop mode disables all circuits within the MAXQ2010 except for the 32kHz crystal amplifier and any circuitry that is
clocked directly by the 32kHz clock. All other on-chip clocks, timers, serial ports, and other peripherals are stopped,
and no code execution occurs. Once in stop mode, the MAXQ2010 is in a near-static state, with power consumption
determined largely by leakage currents.
The RTC always continues to run during stop mode if it was enabled upon stop mode entry. The LCD controller con-
tinues to run during stop mode if the following conditions are true:
• The 32kHz clock is selected as the LCD controller clock source (LCCS = 0).
• The LCD controller is in normal operation mode (OPM = 1).
• The LCD controller is enabled to operate during stop mode (SMO = 1).
Stop mode is invoked by setting the STOP bit to 1. The MAXQ2010 enters stop mode immediately when the STOP bit
is set. Entering stop mode does not affect the setting of the clock control bits; this allows the system to return to its
original operating frequency following stop mode removal.
The processor exits stop mode if any of the following conditions occur. In order to exit stop mode by means of an inter-
rupt, the interrupt must be enabled globally, by module, and locally prior to entering stop mode.
• External reset (from the RST pin)
• Power-on/brownout reset
• External interrupt
• RTC time-of-day or subsecond alarm
• I
2 C start interrupt
• Supply voltage monitor interrupt (SVMSTOP must be set to 1)
Note that exiting stop mode through external reset or power-on reset causes the processor to undergo a normal reset
cycle, as opposed to resuming execution at the point at which it entered stop mode. Exiting stop mode by means of
an interrupt or RTC alarm causes the processor to vector to the interrupt handler routine at IV. Following the completion
of the interrupt handler, execution resumes at the instruction following the one that caused the entry into stop mode.
When the processor exits stop mode, program execution resumes after approximately four FLL oscillator cycles (refer
to the IC data sheet for timing details). The clock source following stop mode exit is selected as follows:
• If FLLSL = 1, the processor continues running from the FLL indefinitely.
• If FLLSL = 0, the processor continues running from the FLL until the high-frequency clock source completes its
65,536-cycle warmup count, at which point it switches over to the high-frequency clock automatically.
Note: The MAXQ2010 powers down parts of the memory interface during stop mode to conserve power. Because
of this, application code must always “re-prime” the active data pointer (DP[0], DP[1], or BP[OFFS]) following
any exit from stop mode before using that data pointer to read from memory. This can be accomplished by:
• Writing a new address (or rewriting the existing address) to the active data pointer.
• Writing to the DPC register to select a new data pointer (or reselect the active data pointer).