Maxim Integrated MAXQ Family Users Guide: MAXQ2010 Supplement - Manual (Page 124)

MAXQ Family User’s Guide:
MAXQ2010 Supplement
22-1
SECTION 22 : I 2 C BUS INTERFACE (SPECIFIC TO MAXQ2010)
The MAXQ2010 provides an inter-IC (I 2 C) communications module that includes master and slave modes. The associ-
ated pins and registers for this interface are listed in Table 22-1 and Table 22-2.
Table 22-1. I 2 C Input and Output Pins
Table 22-2. I 2 C Interface Control Registers
22.1 I 2 C Register Descriptions
The following peripheral registers are used to control the integrated I 2 C peripheral on the MAXQ2010. Addresses for
all registers are given as “Mx[yy],” where x is the module number (from 0 to 15 decimal) and yy is the register index
(from 00h to 1Fh hexadecimal). Fields in the bit definition tables are defined as follows:
• Name: Symbolic names of bits or bit fields in this register.
• Reset: The value of each bit in this register following a standard reset. If this field reads “unchanged,” the given bit
is unaffected by standard reset. If this field reads “s,” the given bit does not have a fixed 0 or 1 reset value because
its value is determined by another internal state or external condition.
• POR: If present this field defines the value of each bit in this register following a power-on reset (as opposed to a
standard reset). Some bits are unaffected by standard resets and are set/cleared by POR only.
• Access: Bits can be read-only (r) or read/write (rw). Any special restrictions or conditions that could apply when
reading or writing this bit are detailed in the bit description.
22.1.1 I 2 C Data Buffer Register (I2CBUF, M3[00h])
Note: ADCONV cannot be written when PMME = 1 and SWB = 0.
I 2 C INTERFACE FUNCTION PIN MULTIPLEXED WITH GPIO
SCL: Clock 24 P6.6
SDA: Data 23 P6.7
REGISTER ADDRESS FUNCTION
I2CBUF M3[00h] I 2 C Data Buffer Register. Interface register for the input and output I 2 C buffers.
I2CST M3[01h] I 2 C Status Register. Contains the interrupt and status flags for the I 2 C interface.
I2CIE M3[02h]
I 2 C Interrupt Enable Register. Contains the interrupt enable bits and control bits for general call
address matching and clock stretching.
I2CCN M3[0Ch] I 2 C Control Register. Contains the control and configuration bits for the I 2 C interface.
I2CCK M3[0Dh] I 2 C Clock Control Register. Defines the SCL high and low clock periods for I 2 C master mode.
I2CTO M3[0Eh]
I 2 C Timeout Register. Enables/disables the master mode timeout when the bus is busy or SCL
is held low by another device longer than the maximum allowed time, and defines the timeout
period.
I2CSLA M3[0Fh]
I 2 C Slave Address Register. Defines the 7-bit address that is recognized by the slave portion of
the I 2 C interface.
Bit # 7 6 5 4 3 2 1 0
Name I2CBUF
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw