Watlow CPC400 - Manual (Page 203)

CPC400 Series User’s Guide Appendix A: Modbus Protocol
Doc. 0600-2900-2000 Watlow Anafaze 189
For example, suppose these eight data bits are contained in
an RTU character frame:
1100 0101
Four bits are set to 1. If even parity is used, the frame’s par-
ity bit will be a 0, resulting in an even quantity of bits (four)
set to 1. If odd parity is used, the parity bit will be set to 1,
resulting in an odd quantity of bits (five) set to 1.
When the message is transmitted, the parity bit is calculat-
ed and applied to the frame of each character. The receiv-
ing device counts the quantity of bits set to 1 and sets an
error if they are not the same as configured for that device.
(All devices on the Modbus network must be configured to
use the same parity check method.)
Note that parity checking can detect an error only if an odd
number of bits are picked up or dropped in a character
frame during transmission. For example, if odd parity
checking is used, and two 1 bits are dropped from a charac-
ter containing three 1 bits, the result is still an odd count.
If no parity checking is used, then the parity bit is not
transmitted and no parity check is made. An additional
stop bit is transmitted to fill out the character frame.
CRC Checking
All messages include an error-checking field that is based
on a cyclical redundancy check (CRC) method. The CRC
field checks the contents of the entire message. It is applied
regardless of any parity check method used for the individ-
ual characters of the message.
The CRC field is two bytes, containing a 16-bit binary val-
ue. The CRC value is calculated by the transmitting device,
which appends the CRC to the message. The receiving de-
vice recalculates a CRC during receipt of the message and
compares the calculated value to the actual value it re-
ceived in the CRC field. If the two values are not equal, an
error results.
The CRC is started by first preloading a 16-bit register to
all 1s. Then a process begins of applying successive 8-bit
bytes of the message to the current contents of the register.
Only the eight bits of data in each character are used for
generating the CRC. Start and stop bits, and the parity bit
if one is used, do not apply to the CRC.
During generation of the CRC, each 8-bit character is ex-
clusive ORed with the register contents. Then the result is
shifted in the direction of the least significant bit (LSB),
with a 0 filled into the most significant bit (MSB) position.
The LSB is extracted and examined. If the LSB was a 1, the
register is then exclusive ORed with the preset, fixed value
A001. If the LSB was a 0, no exclusive OR takes place.
This process is repeated until eight shifts have been per-
formed. After the last shift, the next 8-bit byte is exclusive