Intel 253666-024US User Manual

Page 96

3-50 Vol. 2A

ADDSUBPS—Packed Single-FP Add/Subtract

INSTRUCTION SET REFERENCE, A-M

Operation

xmm1[31:0]

−

xmm2/m128[31:0];

xmm1[63:32]

xmm2/m128[63:32];

xmm1[95:64]

−

xmm2/m128[95:64];

xmm1[127:96]

xmm2/m128[127:96];

Intel C/C++ Compiler Intrinsic Equivalent

ADDSUBPS

__m128 _mm_addsub_ps(__m128 a, __m128 b)

Exceptions

When the source operand is a memory operand, the operand must be aligned on a
16-byte boundary or a general-protection exception (#GP) will be generated.

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Precision, Denormal.

Protected Mode Exceptions

#GP(0)

For an illegal memory operand effective address in the CS, DS,

ES, FS or GS segments.

If a memory operand is not aligned on a 16-byte boundary,

regardless of segment.

#SS(0)

For an illegal address in the SS segment.

#PF(fault-code)

For a page fault.

#NM

If CR0.TS[bit 3] = 1.

#XM

For an unmasked Streaming SIMD Extensions numeric excep-
tion, CR4.OSXMMEXCPT[bit 10] = 1.

#UD

If CR0.EM[bit 2] = 1.
For an unmasked Streaming SIMD Extensions numeric excep-
tion (CR4.OSXMMEXCPT[bit 10] = 0).
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:ECX.SSE3[bit 0] = 0.
If the LOCK prefix is used.

Real Address Mode Exceptions

GP(0)

If any part of the operand would lie outside of the effective

address space from 0 to 0FFFFH.

If a memory operand is not aligned on a 16-byte boundary,

regardless of segment.

#NM

If CR0.TS[bit 3] = 1.