Intel 253666-024US - Manual (Page 182)

3-136 Vol. 2A CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands
INSTRUCTION SET REFERENCE, A-M
CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
A6 CMPS m8, m8 Valid Valid For legacy mode, compare byte at
address DS:(E)SI with byte at
address ES:(E)DI; For 64-bit mode
compare byte at address (R|E)SI to
byte at address (R|E)DI. The status
flags are set accordingly.
A7 CMPS m16, m16 Valid Valid For legacy mode, compare word at
address DS:(E)SI with word at
address ES:(E)DI; For 64-bit mode
compare word at address (R|E)SI
with word at address (R|E)DI. The
status flags are set accordingly.
A7 CMPS m32, m32 Valid Valid For legacy mode, compare dword
at address DS:(E)SI at dword at
address ES:(E)DI; For 64-bit mode
compare dword at address (R|E)SI
at dword at address (R|E)DI. The
status flags are set accordingly.
REX.W + A7 CMPS m64, m64 Valid N.E. Compares quadword at address
(R|E)SI with quadword at address
(R|E)DI and sets the status flags
accordingly.
A6 CMPSB Valid Valid For legacy mode, compare byte at
address DS:(E)SI with byte at
address ES:(E)DI; For 64-bit mode
compare byte at address (R|E)SI
with byte at address (R|E)DI. The
status flags are set accordingly.