Intel 253666-024US - Manual (Page 268)

3-222 Vol. 2A CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Preci-
sion Floating-Point Value
INSTRUCTION SET REFERENCE, A-M
CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to
Scalar Single-Precision Floating-Point Value
Description
Converts a double-precision floating-point value in the source operand (second
operand) to a single-precision floating-point value in the destination operand (first
operand).
The source operand can be an XMM register or a 64-bit memory location. The desti-
nation operand is an XMM register. When the source operand is an XMM register, the
double-precision floating-point value is contained in the low quadword of the register.
The result is stored in the low doubleword of the destination operand, and the upper
3 doublewords are left unchanged. When the conversion is inexact, the value
returned is rounded according to the rounding control bits in the MXCSR register.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).
Operation
DEST[31:0] ← Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0]);
(* DEST[127:32] unchanged *)
Intel C/C++ Compiler Intrinsic Equivalent
CVTSD2SS __m128 _mm_cvtsd_ss(__m128d a, __m128d b)
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal.
Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS,
ES, FS or GS segments.
#SS(0) For an illegal address in the SS segment.
#PF(fault-code) For a page fault.
#NM If CR0.TS[bit 3] = 1.
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
F2 0F 5A /r CVTSD2SS xmm1,
xmm2/m64
Valid Valid Convert one double-precision floating-
point value in xmm2/m64 to one
single-precision floating-point value in
xmm1.