Intel 253666-024US - Manual (Page 202)

3-156 Vol. 2A COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and Set
EFLAGS
INSTRUCTION SET REFERENCE, A-M
COMISD—Compare Scalar Ordered Double-Precision Floating-Point
Values and Set EFLAGS
Description
Compares the double-precision floating-point values in the low quadwords of
operand 1 (first operand) and operand 2 (second operand), and sets the ZF, PF, and
CF flags in the EFLAGS register according to the result (unordered, greater than, less
than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unor-
dered result is returned if either source operand is a NaN (QNaN or SNaN).
Operand 1 is an XMM register; operand 2 can be an XMM register or a 64 bit memory
location.
The COMISD instruction differs from the UCOMISD instruction in that it signals a
SIMD floating-point invalid operation exception (#I) when a source operand is either
a QNaN or SNaN. The UCOMISD instruction signals an invalid numeric exception only
if a source operand is an SNaN.
The EFLAGS register is not updated if an unmasked SIMD floating-point exception is
generated.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).
Operation
RESULT ← OrderedCompare(DEST[63:0] <> SRC[63:0]) {
(* Set EFLAGS *) CASE (RESULT) OF
UNORDERED: ZF,PF,CF ← 111;
GREATER_THAN: ZF,PF,CF ← 000;
LESS_THAN: ZF,PF,CF ← 001;
EQUAL: ZF,PF,CF ← 100;
ESAC;
OF, AF, SF ← 0; }
Intel C/C++ Compiler Intrinsic Equivalents
int _mm_comieq_sd (__m128d a, __m128d b)
int _mm_comilt_sd (__m128d a, __m128d b)
Opcode Instruction 64-Bit Mode Compat/
Leg Mode
Description
66 0F 2F /r COMISD xmm1,
xmm2/m64
Valid Valid Compare low double-precision
floating-point values in xmm1
and xmm2/mem64 and set
the EFLAGS flags accordingly.