Intel 253666-024US User Manual

Page 607

Vol. 2A 3-561

INSTRUCTION SET REFERENCE, A-M

LSL—Load Segment Limit

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0)

If the memory operand effective address referencing the SS

segment is in a non-canonical form.

#GP(0)

If the memory operand effective address is in a non-canonical

form.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and the memory operand effec-

tive address is unaligned while the current privilege level is 3.

#UD

If the LOCK prefix is used.