Intel 253666-024US User Manual

Page 753

Vol. 2A 3-707

INSTRUCTION SET REFERENCE, A-M

MULSS—Multiply Scalar Single-Precision Floating-Point Values

Description

Multiplies the low single-precision floating-point value from the source operand
(second operand) by the low single-precision floating-point value in the destination
operand (first operand), and stores the single-precision floating-point result in the
destination operand. The source operand can be an XMM register or a 32-bit memory
location. The destination operand is an XMM register. The three high-order double-
words of the destination operand remain unchanged. See Figure 10-6 in the Intel®
64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustra-
tion of a scalar single-precision floating-point operation.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).

Operation

DEST[31:0] ← DEST[31:0]

∗

SRC[31:0];

(* DEST[127:32] unchanged *)

Intel C/C++ Compiler Intrinsic Equivalent

MULSS

__m128 _mm_mul_ss(__m128 a, __m128 b)

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Precision, Denormal.

Protected Mode Exceptions

#GP(0)

For an illegal memory operand effective address in the CS, DS,

ES, FS or GS segments.

#SS(0)

For an illegal address in the SS segment.

#PF(fault-code)

For a page fault.

#NM

If CR0.TS[bit 3] = 1.

#XM

If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 1.

Opcode

Instruction

64-Bit

Mode

Compat/

Leg Mode

Description

F3 0F 59 /r

MULSS xmm1,

xmm2/m32

Valid

Multiply the low single-precision floating-

point value in xmm2/mem by the low

single-precision floating-point value in

xmm1.