Intel 253666-024US - Manual (Page 646)

3-600 Vol. 2A MOV—Move
INSTRUCTION SET REFERENCE, A-M
Description
Copies the second operand (source operand) to the first operand (destination
operand). The source operand can be an immediate value, general-purpose register,
segment register, or memory location; the destination register can be a general-
purpose register, segment register, or memory location. Both operands must be the
same size, which can be a byte, a word, or a doubleword.
The MOV instruction cannot be used to load the CS register. Attempting to do so
results in an invalid opcode exception (#UD). To load the CS register, use the far JMP,
CALL, or RET instruction.
If the destination operand is a segment register (DS, ES, FS, GS, or SS), the source
operand must be a valid segment selector. In protected mode, moving a segment
selector into a segment register automatically causes the segment descriptor infor-
mation associated with that segment selector to be loaded into the hidden (shadow)
part of the segment register. While loading this information, the segment selector
and segment descriptor information is validated (see the “Operation” algorithm
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
REX.W + A3 MOV moffs64*,RAX Valid N.E. Move RAX to (offset).
B0+ rb MOV r8, imm8 Valid Valid Move imm8 to r8.
REX + B0+ rb MOV r8 *** , imm8 Valid N.E. Move imm8 to r8.
B8+ rw MOV r16, imm16 Valid Valid Move imm16 to r16.
B8+ rd MOV r32, imm32 Valid Valid Move imm32 to r32.
REX.W + B8+ rd MOV r64, imm64 Valid N.E. Move imm64 to r64.
C6 /0 MOV r/m8, imm8 Valid Valid Move imm8 to r/m8.
REX + C6 /0 MOV r/m8***, imm8 Valid N.E. Move imm8 to r/m8.
C7 /0 MOV r/m16, imm16 Valid Valid Move imm16 to r/m16.
C7 /0 MOV r/m32, imm32 Valid Valid Move imm32 to r/m32.
REX.W + C7 /0 MOV r/m64, imm32 Valid N.E. Move imm32 sign
extended to 64-bits to
r/m64.
NOTES:
* The moffs8, moffs16, moffs32 and moffs64 operands specify a simple offset relative to the seg-
ment base, where 8, 16, 32 and 64 refer to the size of the data. The address-size attribute of the
instruction determines the size of the offset, either 16, 32 or 64 bits.
** In 32-bit mode, the assembler may insert the 16-bit operand-size prefix with this instruction (see
the following “Description” section for further information).
***In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is
used: AH, BH, CH, DH.