Intel 253666-024US - Manual (Page 615)

Vol. 2A 3-569
INSTRUCTION SET REFERENCE, A-M
MASKMOVQ—Store Selected Bytes of Quadword
The MASKMOVQ instruction can be used to improve performance for algorithms that
need to merge data on a byte-by-byte basis. It should not cause a read for owner-
ship; doing so generates unnecessary bandwidth since data is to be written directly
using the byte-mask without allocating old data prior to the store.
In 64-bit mode, the memory address is specified by DS:RDI.
Operation
IF (MASK[7] = 1)
THEN DEST[DI/EDI] ← SRC[7:0] ELSE (* Memory location unchanged *); FI;
IF (MASK[15] = 1)
THEN DEST[DI/EDI +1] ← SRC[15:8] ELSE (* Memory location unchanged *); FI;
(* Repeat operation for 3rd through 6th bytes in source operand *)
IF (MASK[63] = 1)
THEN DEST[DI/EDI +15] ← SRC[63:56] ELSE (* Memory location unchanged *); FI;
Intel C/C++ Compiler Intrinsic Equivalent
void _mm_maskmove_si64(__m64d, __m64n, char * p)
Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS,
ES, FS or GS segments (even if mask is all 0s).
If the destination operand is in a nonwritable segment.
If the DS, ES, FS, or GS register contains a NULL segment
selector.
#SS(0) For an illegal address in the SS segment (even if mask is all 0s).
#PF(fault-code) For a page fault (implementation specific).
#NM If CR0.TS[bit 3] = 1.
#MF If there is a pending FPU exception.
#UD If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE[bit 25] = 0.
If Mod field of the ModR/M byte not 11B.
If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
Real-Address Mode Exceptions
GP(0) If any part of the operand lies outside the effective address
space from 0 to FFFFH. (even if mask is all 0s).
#NM If CR0.TS[bit 3] = 1.