Intel 253666-024US - Manual (Page 200)

3-154 Vol. 2A CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes
INSTRUCTION SET REFERENCE, A-M
Operation
IF (64-Bit Mode and OperandSize = 64)
THEN
IF (RDX:RAX = DEST)
ZF ← 1;
DEST ← RCX:RBX;
ELSE
ZF ← 0;
RDX:RAX ← DEST;
FI
ELSE
IF (EDX:EAX = DEST)
ZF ← 1;
DEST ← ECX:EBX;
ELSE
ZF ← 0;
EDX:EAX ← DEST;
FI;
FI;
Flags Affected
The ZF flag is set if the destination operand and EDX:EAX are equal; otherwise it is
cleared. The CF, PF, AF, SF, and OF flags are unaffected.
Protected Mode Exceptions
#UD If the destination is not a memory operand.
#GP(0) If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment
selector.
#SS(0) If a memory operand effective address is outside the SS
segment limit.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
Real-Address Mode Exceptions
#UD If the destination operand is not a memory location.
#GP If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.