Intel 253666-024US - Manual (Page 100)

3-54 Vol. 2A AND—Logical AND
INSTRUCTION SET REFERENCE, A-M
Description
Performs a bitwise AND operation on the destination (first) and source (second)
operands and stores the result in the destination operand location. The source
operand can be an immediate, a register, or a memory location; the destination
operand can be a register or a memory location. (However, two memory operands
cannot be used in one instruction.) Each bit of the result is set to 1 if both corre-
sponding bits of the first and second operands are 1; otherwise, it is set to 0.
This instruction can be used with a LOCK prefix to allow the it to be executed atomi-
cally.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix
in the form of REX.R permits access to additional registers (R8-R15). Using a REX
prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at
the beginning of this section for encoding data and limits.
Operation
DEST ← DEST AND SRC;
Flags Affected
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the
result. The state of the AF flag is undefined.
Protected Mode Exceptions
#GP(0) If the destination operand points to a non-writable segment.
If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment
selector.
#SS(0) If a memory operand effective address is outside the SS
segment limit.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
#UD If the LOCK prefix is used but the destination is not a memory
operand.
Real-Address Mode Exceptions
#GP If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
#SS If a memory operand effective address is outside the SS
segment limit.