Intel 253666-024US - Manual (Page 196)

3-150 Vol. 2A CMPXCHG—Compare and Exchange
INSTRUCTION SET REFERENCE, A-M
CMPXCHG—Compare and Exchange
Description
Compares the value in the AL, AX, EAX, or RAX register with the first operand (desti-
nation operand). If the two values are equal, the second operand (source operand) is
loaded into the destination operand. Otherwise, the destination operand is loaded
into the AL, AX, EAX or RAX register. RAX register is available only in 64-bit mode.
This instruction can be used with a LOCK prefix to allow the instruction to be
executed atomically. To simplify the interface to the processor’s bus, the destination
operand receives a write cycle without regard to the result of the comparison. The
destination operand is written back if the comparison fails; otherwise, the source
operand is written into the destination. (The processor never produces a locked read
without also producing a locked write.)
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
0F B0/r CMPXCHG r/m8, r8 Valid Valid* Compare AL with r/m8. If
equal, ZF is set and r8 is
loaded into r/m8. Else, clear
ZF and load r/m8 into AL.
REX + 0F B0/r CMPXCHG
r/m8**,r8
Valid N.E. Compare AL with r/m8. If
equal, ZF is set and r8 is
loaded into r/m8. Else, clear
ZF and load r/m8 into AL.
0F B1/r CMPXCHG r/m16,
r16
Valid Valid* Compare AX with r/m16. If
equal, ZF is set and r16 is
loaded into r/m16. Else,
clear ZF and load r/m16
into AX.
0F B1/r CMPXCHG r/m32,
r32
Valid Valid* Compare EAX with r/m32.
If equal, ZF is set and r32 is
loaded into r/m32. Else,
clear ZF and load r/m32
into EAX.
REX.W + 0F B1/r CMPXCHG r/m64,
r64
Valid N.E. Compare RAX with r/m64.
If equal, ZF is set and r64 is
loaded into r/m64. Else,
clear ZF and load r/m64
into RAX.
NOTES:
* See the IA-32 Architecture Compatibility section below.
** In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is
used: AH, BH, CH, DH.