Intel 253666-024US - Manual (Page 241)

Vol. 2A 3-195
INSTRUCTION SET REFERENCE, A-M
CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Double-
word Integers
CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to
Packed Doubleword Integers
Description
Converts two packed double-precision floating-point values in the source operand
(second operand) to two packed signed doubleword integers in the destination
operand (first operand).
The source operand can be an XMM register or a 128-bit memory location. The desti-
nation operand is an XMM register. The result is stored in the low quadword of the
destination operand and the high quadword is cleared to all 0s.
When a conversion is inexact, the value returned is rounded according to the
rounding control bits in the MXCSR register. If a converted result is larger than the
maximum signed doubleword integer, the floating-point invalid exception is raised,
and if this exception is masked, the indefinite integer value (80000000H) is returned.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).
Operation
DEST[31:0] ← Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);
DEST[63:32] ← Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64]);
DEST[127:64] ← 0000000000000000H;
Intel C/C++ Compiler Intrinsic Equivalent
CVTPD2DQ __m128i _mm_cvtpd_epi32(__m128d a)
SIMD Floating-Point Exceptions
Invalid, Precision.
Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS,
ES, FS or GS segments.segments.
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
F2 0F E6 CVTPD2DQ xmm1,
xmm2/m128
Valid Valid Convert two packed double-
precision floating-point values
from xmm2/m128 to two
packed signed doubleword
integers in xmm1.