Intel 253666-024US - Manual (Page 672)

3-626 Vol. 2A MOVDQU—Move Unaligned Double Quadword
INSTRUCTION SET REFERENCE, A-M
Protected Mode Exceptions
#AC(0) If alignment checking is enabled and an unaligned memory
reference is made.
#GP(0) If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
#SS(0) If a memory operand effective address is outside the SS
segment limit.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE[bit 25] = 0.
#PF(fault-code) If a page fault occurs.
Real-Address Mode Exceptions
#GP(0) If any part of the operand lies outside of the effective address
space from 0 to FFFFH.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE[bit 25] = 0.
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
Same exceptions as in real address mode.
#AC(0)
If alignment checking is enabled and an unaligned memory
reference is made.
#PF(fault-code) For a page fault.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#AC(0) If alignment checking is enabled and an unaligned memory
reference is made.
#SS(0) If a memory address referencing the SS segment is in a non-
canonical form.
#GP(0) If the memory address is in a non-canonical form.
#PF(fault-code) For a page fault.
#NM If CR0.TS[bit 3] = 1.