Intel 253666-024US - Manual (Page 449)

Vol. 2A 3-403
INSTRUCTION SET REFERENCE, A-M
FSUBR/FSUBRP/FISUBR—Reverse Subtract
the register stack being popped. In some assemblers, the mnemonic for this instruc-
tion is FSUBR rather than FSUBRP.
The FISUBR instructions convert an integer source operand to double extended-
precision floating-point format before performing the subtraction.
The following table shows the results obtained when subtracting various classes of
numbers from one another, assuming that neither overflow nor underflow occurs.
Here, the DEST value is subtracted from the SRC value (SRC − DEST = result).
When the difference between two operands of like sign is 0, the result is +0, except for
the round toward −∞ mode, in which case the result is −0. This instruction also guaran-
tees that +0 − (−0) = +0, and that −0 − (+0) = −0. When the source operand is an integer 0,
it is treated as a +0.
When one operand is ∞, the result is ∞ of the expected sign. If both operands are ∞ of
the same sign, an invalid-operation exception is generated.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
IF Instruction = FISUBR
THEN
DEST ← ConvertToDoubleExtendedPrecisionFP(SRC) − DEST;
ELSE (* Source operand is floating-point value *)
DEST ← SRC − DEST; FI;
Table 3-44. FSUBR/FSUBRP/FISUBR Results
SRC
− ∞ −F or −I −0 +0 +F or +I + ∞ NaN
− ∞ * + ∞ + ∞ + ∞ + ∞ + ∞ NaN
−F − ∞ ±F or ±0 −DEST −DEST +F + ∞ NaN
DEST −0 − ∞ SRC ±0 +0 SRC + ∞ NaN
+0 − ∞ SRC −0 ±0 SRC + ∞ NaN
+F − ∞ −F −DEST −DEST ±F or ±0 + ∞ NaN
+ ∞ − ∞ − ∞ − ∞ − ∞ − ∞ * NaN
NaN NaN NaN NaN NaN NaN NaN NaN
NOTES:
F Means finite floating-point value.
I Means integer.
* Indicates floating-point invalid-arithmetic-operand (#IA) exception.