Intel 253666-024US User Manual

Page 433

Vol. 2A 3-387

INSTRUCTION SET REFERENCE, A-M

FST/FSTP—Store Floating Point Value

If the destination operand is a non-empty register, the invalid-operation exception is
not generated.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

DEST ← ST(0);

IF Instruction

FSTP

THEN

PopRegisterStack;

FI;

FPU Flags Affected

Set to 0 if stack underflow occurred.
Indicates rounding direction of if the floating-point inexact

exception (#P) is generated: 0 ← not roundup; 1 ← roundup.

C0, C2, C3

Undefined.

Floating-Point Exceptions

#IS

Stack underflow occurred.

#IA

Source operand is an SNaN value or unsupported format. Does

not occur if the source operand is in double extended-precision
floating-point format.

Result is too small for the destination format.

Result is too large for the destination format.

Value cannot be represented exactly in destination format.

Protected Mode Exceptions

#GP(0)

If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS,

ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register is used to access memory and it

contains a NULL segment selector.

#SS(0)

If a memory operand effective address is outside the SS

segment limit.

#NM

CR0.EM[bit 2] or CR0.TS[bit 3] = 1.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory

reference is made while the current privilege level is 3.

#UD

If the LOCK prefix is used.