Intel 253666-024US - Manual (Page 190)

3-144 Vol. 2A CMPSD—Compare Scalar Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-M
CMPSD for greater-than-or-equal__m128d _mm_cmpge_sd(__m128d a, __m128d b)
CMPSD for inequality
__m128d _mm_cmpneq_sd(__m128d a, __m128d b)
CMPSD for not-less-than __m128d _mm_cmpnlt_sd(__m128d a, __m128d b)
CMPSD for not-greater-than __m128d _mm_cmpngt_sd(__m128d a, __m128d b)
CMPSD for not-greater-than-or-equal__m128d _mm_cmpnge_sd(__m128d a, __m128d b)
CMPSD for ordered
__m128d _mm_cmpord_sd(__m128d a, __m128d b)
CMPSD for unordered __m128d _mm_cmpunord_sd(__m128d a, __m128d b)
CMPSD for not-less-than-or-equal__m128d _mm_cmpnle_sd(__m128d a, __m128d b)
SIMD Floating-Point Exceptions
Invalid if SNaN operand, Invalid if QNaN and predicate as listed in above table,
Denormal.
Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS,
ES, FS or GS segments.
#SS(0) For an illegal address in the SS segment.
#PF(fault-code) For a page fault.
#NM If CR0.TS[bit 3] = 1.
#XM If an unmasked SIMD floating-point exception and CR4.OSXM-
MEXCPT[bit 10] = 1.
#UD If an unmasked SIMD floating-point exception and CR4.OSXM-
MEXCPT[bit 10] = 0.
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE2[bit 26] = 0.
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
Real-Address Mode Exceptions
#GP(0) If any part of the operand lies outside the effective address
space from 0 to FFFFH.
#NM If CR0.TS[bit 3] = 1.
#XM If an unmasked SIMD floating-point exception and CR4.OSXM-
MEXCPT[bit 10] = 1.
#UD If an unmasked SIMD floating-point exception and CR4.OSXM-
MEXCPT[bit 10] = 0.
If CR0.EM[bit 2] = 1.