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Intel 253666-024US User Manual

Page 468

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3-422 Vol. 2A

FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 State

INSTRUCTION SET REFERENCE, A-M

Here, a 1 is saved for any valid, zero, or special tag, and a 0 is saved for any empty
tag.
The operation of the FXSAVE instruction differs from that of the FSAVE instruction,
the as follows:

FXSAVE instruction does not check for pending unmasked floating-point
exceptions. (The FXSAVE operation in this regard is similar to the operation of the
FNSAVE instruction).

After the FXSAVE instruction has saved the state of the x87 FPU, MMX
technology, XMM, and MXCSR registers, the processor retains the contents of the
registers. Because of this behavior, the FXSAVE instruction cannot be used by an
application program to pass a “clean” x87 FPU state to a procedure, since it
retains the current state. To clean the x87 FPU state, an application must
explicitly execute an FINIT instruction after an FXSAVE instruction to reinitialize
the x87 FPU state.

The format of the memory image saved with the FXSAVE instruction is the same
regardless of the current addressing mode (32-bit or 16-bit) and operating mode
(protected, real address, or system management). This behavior differs from the
FSAVE instructions, where the memory image format is different depending on
the addressing mode and operating mode. Because of the different image
formats, the memory image saved with the FXSAVE instruction cannot be
restored correctly with the FRSTOR instruction, and likewise the state saved with
the FSAVE instruction cannot be restored correctly with the FXRSTOR instruction.

The FSAVE format for FTW can be recreated from the FTW valid bits and the stored
80-bit FP data (assuming the stored data was not the contents of MMX technology
registers) using Table 3-50.

Table 3-50. Recreating FSAVE Format

Exponent

all 1’s

Exponent

all 0’s

Fraction

all 0’s

J and M

bits

FTW valid

bit

x87 FTW

0

0

0

0x

1

Special

10

0

0

0

1x

1

Valid

00

0

0

1

00

1

Special

10

0

0

1

10

1

Valid

00

0

1

0

0x

1

Special

10

0

1

0

1x

1

Special

10

0

1

1

00

1

Zero

01

0

1

1

10

1

Special

10

1

0

0

1x

1

Special

10

1

0

0

1x

1

Special

10