Intel 253666-024US - Manual (Page 253)

Vol. 2A 3-207
INSTRUCTION SET REFERENCE, A-M
CVTPI2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-
Point Values
CVTPI2PS—Convert Packed Doubleword Integers to Packed Single-
Precision Floating-Point Values
Description
Converts two packed signed doubleword integers in the source operand (second
operand) to two packed single-precision floating-point values in the destination
operand (first operand).
The source operand can be an MMX technology register or a 64-bit memory location.
The destination operand is an XMM register. The results are stored in the low quad-
word of the destination operand, and the high quadword remains unchanged. When
a conversion is inexact, the value returned is rounded according to the rounding
control bits in the MXCSR register.
This instruction causes a transition from x87 FPU to MMX technology operation (that
is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all
0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is
pending, the exception is handled before the CVTPI2PS instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).
Operation
DEST[31:0] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
DEST[63:32] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32]);
(* High quadword of destination unchanged *)
Intel C/C++ Compiler Intrinsic Equivalent
CVTPI2PS __m128 _mm_cvtpi32_ps(__m128 a, __m64 b)
SIMD Floating-Point Exceptions
Precision.
Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS,
ES, FS or GS segments.
#SS(0) For an illegal address in the SS segment.
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
0F 2A /r CVTPI2PS xmm,
mm/m64
Valid Valid Convert two signed doubleword
integers from mm/m64 to two single-
precision floating-point values in xmm.