Intel 253666-024US - Manual (Page 212)

3-166 Vol. 2A CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-M
0AH EAX Bits 07 - 00: Version ID of architectural performance monitoring
Bits 15- 08: Number of general-purpose performance monitoring
counter per logical processor
Bits 23 - 16: Bit width of general-purpose, performance monitoring
counter
Bits 31 - 24: Length of EBX bit vector to enumerate architectural per-
formance monitoring events
EBX Bit 0: Core cycle event not available if 1
Bit 1: Instruction retired event not available if 1
Bit 2: Reference cycles event not available if 1
Bit 3: Last-level cache reference event not available if 1
Bit 4: Last-level cache misses event not available if 1
Bit 5: Branch instruction retired event not available if 1
Bit 6: Branch mispredict retired event not available if 1
Bits 31- 07: Reserved = 0
ECX
EDX
Reserved = 0
Bits 04 - 00: Number of fixed-function performance counters (if Ver-
sion ID > 1)
Bits 12- 05: Bit width of fixed-function performance counters (if Ver-
sion ID > 1)
Reserved = 0
Extended Function CPUID Information
80000000H EAX Maximum Input Value for Extended Function CPUID Information (see
Table 3-13).
EBX
ECX
EDX
Reserved
Reserved
Reserved
80000001H EAX
EBX
ECX
Extended Processor Signature and Extended Feature Bits.
Reserved
Bit 0: LAHF/SAHF available in 64-bit mode
Bits 31-1 Reserved
Table 3-12. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value Information Provided about the Processor