Intel 253666-024US - Manual (Page 371)

Vol. 2A 3-325
INSTRUCTION SET REFERENCE, A-M
FICOM/FICOMP—Compare Integer
FICOM/FICOMP—Compare Integer
Description
Compares the value in ST(0) with an integer source operand and sets the condition
code flags C0, C2, and C3 in the FPU status word according to the results (see table
below). The integer value is converted to double extended-precision floating-point
format before the comparison is made.
These instructions perform an “unordered comparison.” An unordered comparison
also checks the class of the numbers being compared (see “FXAM—ExamineModR/M”
in this chapter). If either operand is a NaN or is in an undefined format, the condition
flags are set to “unordered.”
The sign of zero is ignored, so that –0.0 ← +0.0.
The FICOMP instructions pop the register stack following the comparison. To pop the
register stack, the processor marks the ST(0) register empty and increments the
stack pointer (TOP) by 1.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
CASE (relation of operands) OF
ST(0) > SRC: C3, C2, C0 ← 000;
ST(0) < SRC: C3, C2, C0 ← 001;
ST(0) = SRC: C3, C2, C0 ← 100;
Unordered: C3, C2, C0 ← 111;
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
DE /2 FICOM m16int Valid Valid Compare ST(0) with m16int.
DA /2 FICOM m32int Valid Valid Compare ST(0) with m32int.
DE /3 FICOMP m16int Valid Valid Compare ST(0) with m16int and pop
stack register.
DA /3 FICOMP m32int Valid Valid Compare ST(0) with m32int and pop
stack register.
Table 3-31. FICOM/FICOMP Results
Condition C3 C2 C0
ST(0) > SRC 0 0 0
ST(0) < SRC 0 0 1
ST(0) = SRC 1 0 0
Unordered 1 1 1