Intel 253666-024US - Manual (Page 178)

3-132 Vol. 2A CMPPS—Compare Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-M
The greater-than relations not implemented by the processor require more than one
instruction to emulate in software and therefore should not be implemented as
pseudo-ops. (For these, the programmer should reverse the operands of the corre-
sponding less than relations and use move instructions to ensure that the mask is
moved to the correct destination register and that the source operand is left intact.)
Operation
CASE (COMPARISON PREDICATE) OF
0: OP ← EQ;
1: OP ← LT;
2: OP ← LE;
3: OP ← UNORD;
4: OP ← NE;
5: OP ← NLT;
6: OP ← NLE;
7: OP ← ORD;
EASC;
CMP0 ← DEST[31:0] OP SRC[31:0];
CMP1 ← DEST[63:32] OP SRC[63:32];
CMP2 ← DEST [95:64] OP SRC[95:64];
CMP3 ← DEST[127:96] OP SRC[127:96];
IF CMP0 = TRUE
THEN DEST[31:0] ← FFFFFFFFH;
ELSE DEST[31:0] ← 00000000H; FI;
IF CMP1 = TRUE
THEN DEST[63:32] ← FFFFFFFFH;
ELSE DEST[63:32] ← 00000000H; FI;
IF CMP2 = TRUE
Table 3-9. Pseudo-Ops and CMPPS
Pseudo-Op Implementation
CMPEQPS xmm1, xmm2 CMPPS xmm1, xmm2, 0
CMPLTPS xmm1, xmm2 CMPPS xmm1, xmm2, 1
CMPLEPS xmm1, xmm2 CMPPS xmm1, xmm2, 2
CMPUNORDPS xmm1, xmm2 CMPPS xmm1, xmm2, 3
CMPNEQPS xmm1, xmm2 CMPPS xmm1, xmm2, 4
CMPNLTPS xmm1, xmm2 CMPPS xmm1, xmm2, 5
CMPNLEPS xmm1, xmm2 CMPPS xmm1, xmm2, 6
CMPORDPS xmm1, xmm2 CMPPS xmm1, xmm2, 7